View ICS9250-37_84368.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS932S203
Frequency Generator with 133MHz Differential CPU Clocks
Recommended Application: Servers based on Intel CK408 processors Output Features: * 4 Differential CPU Clock Pairs @ 3.3V * 7 PCI (3.3V) @ 33.3MHz * 3 PCI_F (3.3V) @ 33.3MHz * 1 USB (3.3V) @ 48MHz * 1 DOT (3.3V) @ 48MHz * 1 REF (3.3V) @ 14.318MHz * 1 3V66 (3.3V) @ 66.6MHz * 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz * 3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN or 66.6MHz * 1 66MHz_IN/3V66 (3.3V) @ Input/66MHz Features: * Supports spread spectrum modulation, down spread 0 to -0.5%. * Efficient power management scheme through PD# and PCI_STOP#. * Uses external 14.318MHz crystal * Stop clocks and functional control available through SMBus interface. Key Specifications: * CPU Output Jitter <150ps * 3V66 Output Jitter <250ps * CPU Output Skew <150ps
Pin Configuration
56-Pin 300mil SSOP/TSSOP
* These inputs have 150K internal pull-up resistor to VDD.
Block Diagram
Functionality
CPU (MHz) 100 133.3 100 133.3 Hi-Z Tclk/2 3V66 (MHz) 66.6 66.6 66.6 66.6 Hi-Z Tclk/4 66Buff[2:0] 3V66[4:2] (MHz) 66.6 In path 66. In path 66.6 66.6 Hi-Z Tclk/4 PCI_F PCI (MHz) 66.6 in/2 66.6 in/2 33.3 33.3 Hi-Z Tclk/8
FS1 FS0 1 1 0 0 mid mid 0 1 0 1 0 1
0601E--12/22/04
ICS932S203
Pin Configuration
PIN NUMBER
1, 8, 14, 19, 26, 32, 37, 46, 50 2 3 7, 6, 5 4, 9, 15, 20, 27, 31, 36, 41, 47 18, 17, 16, 13, 12,11, 10 23, 22, 21 24 25
PIN NAME
VDD X1 X2 PCICLK_F (2:0) GND PCICLK (6:0) 66MHz_OUT (2:0) 3V66 (4:2) 66MHz_IN 3V66_5 PD#
TYPE
PWR X2 Cr ystal Input X1 Cr ystal Output OUT PWR OUT OUT OUT IN OUT IN 3.3V power supply 14.318MHz Cr ystal input 14.318MHz Cr ystal output
DESCRIPTION
Free running PCI clock not affected by PCI_STOP# for power management. Ground pins for 3.3V supply PCI clock outputs 66MHz buffered 66MHz_OUT from 66MHz_IN input. 66MHz reference clocks, from internal VCO 66MHz input to buffered 66MHz_OUT and PCI clocks 66MHz reference clock, from internal VCO Invokes power-down mode. Active Low.
28
Vtt_PWRGD#
IN I/O IN
OUT IN OUT OUT OUT IN OUT IN OUT OUT OUT
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS[0:2] and MULTISEL0 inputs are valid and are ready to be sampled (active low)
Data pin for SMBus circuitr y 5V tolerant Clock pin of SMBus circuitr y 5V tolerant 66MHz reference clocks, from internal VCO Halts PCICLK clocks at logic 0 level, when input low except PCICLK_F which are free running 3.3V output selectable through I2C to be 66MHz from internal VCO or 48MHz (non-SSC) 48MHz output clock for DOT 48MHz output clock for USB Special 3.3V input for Mode selection This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. MULTSEL0 input is sensed on power-up and then internally latched prior to the pin being used for output on 3V 14.318MHz clocks. "Complementar y" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. 14.318MHz reference clock.
29 30 33 34 35 38 39 40, 55 42 43 44, 48, 51, 53 45, 49, 52, 54 56
SDATA SCLK 3V66_0 PCI_STOP# 3V66_1/VCH_CLK 48MHz_DOT 48MHz_USB FS (1:0) I REF MULTSEL0 CPUCLKC (3:0) CPUCLKT (3:0) REF
Power Groups
(Analog) VDDA = PLL1 VDD48 = 48MHz, PLL VDDREF = VDD for Xtal, POR (Digital) VDDPCI VDD3V66 VDDCPU
0601E--12/22/04
2
ICS932S203
Frequency Select Table
FS2 1 1 0 0 mid mid FS1 0 1 0 1 0 1 CPU 100 133.3 100 133.3 Hi-Z Tclk/2 3V66 (1:0) 66.6 66.6 66.6 66.6 Hi-Z Tclk/4 66Buff (2:0) / 3V66 (4:2) 66.6 In path 66.6 In path 66.6 66.6 Hi-Z Tclk/4 66 In / 3V66_5 66.6 IN 66.6 IN 66.6 66.6 Hi-Z Tclk/4 PCI 66.6 in/2 66.6 in/2 33.3 33.3 Hi-Z Tclk/8 REF 14.318 14.318 14.318 14.318 Hi-Z Tclk USB, DOT 48 48 48 48 Hi-Z Tclk/2 note Buffer mode 66 Buffer mode 66 Driven 66 Driven 66 Tri-state outputs Tclk is at X1 input
Host Swing Select Functions
MULTISEL0 Board Target Trace/Term Z 50 ohms 50 ohms Reference R, Iref = VDD/(3*Rr) Rr = 221 1%, Iref = 5.00mA Rr = 475 1%, Iref = 2.32mA Output Current Ioh = 4* I REF Ioh = 6* I REF Voh @ Z
0 1
1.0V @ 50 0.7V @ 50
0601E--12/22/04
3
ICS932S203
Byte 0: Control Register
Bit Bit 0 Bit 1 Bit 2 B it 3 Bit 4 Bit 5 Bit 6 B it 7
Pin# 55 40 34 35 -
Name FS0 FS1 PCI_STOP#3
PW D 1 X X X 1
Type R R R
3V66_1/VCH Spread Enabled
0 0 0
RW
Description (Reserved) Reflects the value of FS0 pin sampled on power up Reflects the value of FS1 pin sampled on power up Hardware mode: Reflects the value of PCI_STOP# pin sampled on PWD (Reserved) VCH Select 66MHz/48MHz 0=66MHz, 1=48MHz (Reserved) 0=Spread Off, 1=Spread On
RW
Byte 1: Control Register
Bit Bit 0 Bit 1 Bit 2 B it 3 B it 4 B it 5 Bit 6 Bit 7
Pin# 52, 51 49, 48 45, 44 5 2, 51 49, 48 45, 44 53, 54 43
Name CPUCLKT0 CPUCLKC0 CPUCLKT1 CPUCLKC1 CPUCLKT2 CPUCLKC2
PWD 1 1 1 0 0 0
Type RW RW RW RW R
Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled Reser ved Reser ved Reser ved 0=Disabled 1=Enabled Reflects the current value of MULTSEL0
CPUCLKT3 CPUCLKC3 MULTSEL0
1 X
Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default 3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP functionality via SMBus Byte 0 Bit 3. In Hardware mode it is not allowed to write to the SMBus Byte 0 Bit3. In Software mode it is not allowed to pull the external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix these modes. In Hardware mode the SMBus byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in PCI_STOP mode. Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (SMBus Byte 0 Bit 3 = 0)].
0601E--12/22/04
4
ICS932S203
Byte 2: Control Register
Bit Bit 0 Bit 1 Bit 2 B it 3 B it 4 Bit 5 B it 6 Bit 7
Pin# 10 11 12 13 16 17 18 -
Name PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 -
PWD 1 1 1 1 1 1 1 0
Type RW RW RW RW RW RW RW -
Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled (Reserved)
Byte 3: Control Register
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Pin# 5 6 7 5 6 7 39 38
Name PCICLK_F0 PCICLK_F1 PCICLK_F2 PCICLK_F0 PCICLK_F1 PCICLK_F2 48MHz_USB 48MHz_DOT
PWD 1 1 1 0 0 0 1 1
Type RW RW RW RW RW RW RW RW
Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled Allow control of PCICLK_F0 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running Allow control of PCICLK_F1 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running Allow control of PCICLK_F2 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running 0=Disabled 1=Enabled 0=Disabled 1=Enabled
Byte 4: Control Register
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Pin# 21 22 23 24 35 33 -
Name 66MHz_OUT0/3V66-2 66MHz_OUT0/3V66-3 66MHz_OUT0/3V66-4 3V66_5 3V66_1/VCH_CLK 3V66_0 -
PWD 1 1 1 1 1 1 0 0
Type RW RW RW RW RW RW R R
Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled (Reserved) (Reserved)
Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default
0601E--12/22/04
5
ICS932S203
Byte 5: Programming Edge Rate (1 = enable, 0 = disable)
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Pin# X X X X X X X X
Name 48MHz_USB 48MHz_USB 48MHz_DOT 48MHz_DOT -
PWD 0 0 0 0 0 0 0 0
Type RW RW RW RW -
Description USB edge rate cntrol USB edge rate cntrol DOT edge rate control DOT edge rate control (Reserved) (Reserved) (Reserved) (Reserved)
Byte 6: Vendor ID Register (1 = enable, 0 = disable)
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Pin# X X X X X X X X
Name Vendor ID Bit0 Vendor ID Bit1 Vendor ID Bit2 Vendor ID Bit3 Revision ID Bit0 Revision ID Bit1 Revision ID Bit2 Revision ID Bit3
PWD 1 0 0 0 X X X X
Type R R R R R R R R
Description (Reserved) (Reserved) (Reserved) (Reserved) Revision ID values will be based on individual device's revision
Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default
0601E--12/22/04
6
ICS932S203
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current I IL2 Operating Supply Current I DD3.3OP I DD3.3OP Powerdown Current Input Frequency Pin Inductance Input Capacitance1 Transition time Settling time1 Clk Stabilization1 Delay 1
1 1
SYMBOL CONDITIONS VIH VIL VIN = VDD I IH I IL1 VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = Full load; Select @ 100 MHz CL =Full load; Select @ 133 MHz VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins To 1st crossing of target frequency From 1st crossing to 1% target frequency
MIN 2 VSS - 0.3 -5 -5 -200 229 220
TYP
MAX UNITS VDD + 0.3 V 0.8 V 5 mA mA
230 233 14.318
360 360 60 7 5 6 45 3 3 3 10 10
mA mA mA MHz nH pF pF pF ms ms ms ns ns
I DD3.3PD Fi Lpin CIN COUT CINX Ttrans Ts
27
TSTAB From VDD = 3.3 V to 1% target frequency t PZH,t PZL Output enable delay (all outputs) t PHZ,t PLZ Output disable delay (all outputs)
1 1
Guaranteed by design, not 100% tested in production.
0601E--12/22/04
7
ICS932S203
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo
1
CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 200MHz nominal 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V
MIN 3000 660 -150 -300 250
TYP
MAX
UNITS
NOTES 1 1
VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm
770 5 756 -7 350 12
850 mV 150 1150 550 140 300 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps
1 1 1 1 1 1,2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1
Average period
Tperiod
Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle
Tabsmin tr tf d-tr d-tf dt3
-300 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 4.8735 5.8732 7.3728 9.8720 175 175
332 344 30 30
700 700 125 125
Measurement from differential 45 49 55 % wavefrom tsk3 VT = 50% Skew 8 100 ps Measurement from differential tjcyc-cyc 60 150 ps Jitter, Cycle to cycle wavefrom 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz
0601E--12/22/04
8
ICS932S203
Electrical Characteristics - PCICLK Un-Buffered Mode
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 1 VO = VDD*(0.5) Output Impedance RDSP1 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf1 1 Duty Cycle VT = 1.5 V dt1 1 VT = 1.5 V Skew tsk1 1 VT = 1.5 V tjcyc-cyc Jitter,cycle to cyc
1
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 33
MAX 55 0.55 -33 38 0.5to 2 0.5 to 2 55 500 500
1.32 1.39 52 247 111
UNITS MHz V V mA mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK Buffered Mode
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance RDSP11 VO = VDD*(0.5) Output High Voltage VOH1 IOH = -1 mA IOL = 1 mA Output Low Voltage VOL1 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL1 Rise Time tr11 VOL = 0.4 V, VOH = 2.4 V 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V Duty Cycle VT = 1.5 V dt11 1 Skew tsk1 VT = 1.5 V tjcyc-cyc1 VT = 1.5 V Jitter,cycle to cyc
1
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 33
MAX 55 0.55 -33 38 0.5to 2 0.5 to 2 55 500 500
1.29 1.32 51.9 209 107
UNITS MHz V V mA mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
0601E--12/22/04
9
ICS932S203
Electrical Characteristics - 3V66 -Un-Buffered Mode: 3V66 [5:0]
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 1 Output Impedance RDSP1 VO = VDD*(0.5) 1 Output High Voltage VOH IOH = -1 mA 1 Output Low Voltage VOL IOL = 1 mA 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL 1 VOL = 0.4 V, VOH = 2.4 V Rise Time tr1 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 1 Duty Cycle VT = 1.5 V dt1 Skew Jitter
1
MIN 12 2.4 -33 30 0.5 0.5 45
TYP MAX UNITS 66.66 MHz 33 55 V 0.55 V -33 mA 38 mA 1.38 2 ns 1.45 2 ns % 54.4 55 90 128 250 250 ps ps
tsk1 1 tjcyc-cyc
1
VT = 1.5 V VT = 1.5 V 3V66
Guaranteed by design, not 100% tested in production.
Electrical Characteristics- 3V66 - Buffered Mode: 3V66 [1:0] 66MHz_OUT [2:0]
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 1 VO = VDD*(0.5) Output Impedance RDSP1 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf1 1 Duty Cycle VT = 1.5 V dt1 Skew Jitter Skew Jitter
1
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 66.66 33
MAX 55 0.55 -33 38 2 2 55 250 300 250 300
1.44 1.36 54.6 105 121 169 89
UNITS MHz W V V mA mA ns ns % ps ps ps ps
tsk1
1 1
VT = 1.5 V
3V66 [1:0]
tjcyc-cyc 1 tsk1 1 tjcyc-cyc
VT = 1.5 V 3V66 [1:0] VT = 1.5 V 66MHz_OUT [2:0] VT = 1.5 V 66MHz_OUT [2:0]
Guaranteed by design, not 100% tested in production.
0601E--12/22/04
10
ICS932S203
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 1 Output Impedance RDSP1 VO = VDD*(0.5) 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL 1 48DOT Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 VOH = 2.4 V, VOL = 0.4 V 48DOT Fall Time tf1 1 VOL = 0.4 V, VOH = 2.4 V VCH 48 USB Rise Time tr1 1 VOH = 2.4 V, VOL = 0.4 V VCH 48 USB Fall Time tf1 48 DOT Duty Cycle VCH 48 USB Duty Cycle 48 DOT Jitter VCH Jitter
1
MIN 20 2.4 -29 29 0.5 0.5 1 1 45 45
TYP 48 48
MAX 60 0.4 -23 27 1 1 2 2 55 55 350 350
0.6 0.8 1.2 1.3 52.8 53.5 183 223
UNITS MHz V V mA mA ns ns ns ns % % ps ps
dt1 dt1
1 1
VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
1 tjcyc-cyc 1 tjcyc-cyc
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 1 Output Impedance RDSP1 VO = VDD*(0.5) 1 Output High Voltage VOH IOH = -1 mA 1 Output Low Voltage VOL IOL = 1 mA 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 1 Duty Cycle VT = 1.5 V dt1 1 tjcyc-cyc VT = 1.5 V Jitter
1
MIN 20 2.4 -29 29 1 1 45
TYP 48
1.25 1.15 53 723
UNITS MHz 60 V 0.4 V -23 mA 27 mA 2 ns 2 ns % 55 1000 ps
MAX
Guaranteed by design, not 100% tested in production.
0601E--12/22/04
11
ICS932S203
General SMBus serial interface information
The information in this section assumes familiarity with SMBus programming. For more information, contact ICS for an SMBus software program.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
* * * * * * * *
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
ACK
Byte 1
Byte 1
ACK
ACK
Byte 2
Byte 2
ACK
ACK
Byte 3
Byte 3
ACK
ACK
Byte 4
Byte 4
ACK
ACK
Byte 5
Byte 5
ACK
ACK
Byte 6
Byte 6
ACK
ACK Stop Bit
Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, SMBus component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator SMBus interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
0601E--12/22/04
12
ICS932S203
Buffered Mode - 3V66[0:1], 66MHz_IN, 66MHz_OUT[0:2] and PCI Phase Relationship All 3V66 clocks are to be in phase with each other. All 66MHz_OUT clocks are to be in phase with each other. There is NO phase relationship between the 3V66 clocks and the 66MHz_OUT and PCI clocks. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci. The 66MHz_IN to 66MHz_OUT delay is shown in the figure below and is specified to be within a min and max propagation value.
66MHz_IN 66MHz_OUT
Tpd
Tpci PCICLK_F 3V66 No Relationship
Group Skews at Common Transition Edges: (Buffered Mode)
GROUP 3V66 66MHz_OUT PCI 66MHz_IN 66MHz_OUT 66MHz_OUT to PCI
1
SYMBOL 3V66 66OUT PCI Tpd Tpci
CONDITIONS 3V66 (1:0) pin to pin skew 66MHz_OUT (2:0) pin to pin skew PCI_F (2:0) and PCI (6:0) pin to pin skew Propogation delay from 66MHz_IN to 66MHz_OUT (2:0) 66MHz_OUT (2:0) leads 33 MHz PCI
MIN 0 0 0 2.5 1.5
TYP
MAX UNITS 500 175 500 4.5 3.5 ps ps ps ns ns
Guaranteed by design, not 100% tested in production.
0601E--12/22/04
13
ICS932S203
Un-Buffered Mode 3V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci.
3V66 (1:0) 3V66 (4:2) 3V66_5 PCICLK_F (2:0) PCICLK (6:0) Tpci
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP 3V66 PCI 3V66 to PCI
1
SYMBOL CONDITIONS 3V66 3V66 (5:0) pin to pin skew PCI PCI_F (2:0) and PCI (6:0) pin to pin skew S3V66-PCI 3V66 (5:0) leads 33MHz PCI
MIN 0 0 1.5
TYP
MAX UNITS 500 ps 500 ps 3.5 ns
Guaranteed by design, not 100% tested in production.
PCI_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition.
Assertion of PCI_STOP# Waveforms
PCI_STOP# PCI_F[2:0] 33MHz PCI[6:0] 33MHz
0601E--12/22/04
14
ICS932S203
PD# - Assertion (transition from logic "1" to logic "0") When PD# is sampled low by two consecutive rising edges of CPU clock then all clock outputs except CPU clocks must be held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with a value of 2x Iref, and CPUC undriven. Note the example below shows CPU = 100MHz, this diagram and description is applicable for all valid CPU frequencies 66, 100, 133, 200MHz. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Power Down Assertion of Waveforms - Buffered Mode
0ns PD# CPUT 100MHz CPUC 100MHz 3V66MHz 66MHz_IN 66MHz_OUT PCI 33MHz USB 48MHz REF 14.318MHz 25ns 50ns
PD# Functionality
CPU_STOP# 1 0
CPUT Normal iref * Mult
CPUC Normal Float
3V66 66MHz Low
66MHz_OUT 66MHz_IN Low
PCICLK_F PCICLK 66MHz_IN Low
PCICLK 66MHz_IN Low
USB/DOT 48MHz 48MHz Low
0601E--12/22/04
15
ICS932S203
N
c
SYMBOL
L
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 2.413 0.203 0.203 2.794 0.406 0.343 .095 .008 .008 .110 .016 .0135
A
INDEX AREA E1 E
A1 b c D E
0.127 0.254 SEE VARIATIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE VARIATIONS .395 .291 .015 .420 .299 .025
12 D h x 45
E1 e h L N
0.635 BASIC 0.508 1.016 SEE VARIATIONS 0 8
0.025 BASIC .020 .040 SEE VARIATIONS 0 8
A A1
VARIATIONS
-C-
N 56
D mm. MIN 18.288 MAX 18.542 MIN .720
D (inch) MAX .730
6/1/00 REV B
e
b
SEATING PLANE .10 (.004) C
JEDEC MO-118 DOC# 10-0034
300 mil SSOP
Ordering Information
ICS932S203yFLFT
Example:
ICS XXXX y F Lx T
Designation for tape and reel packaging Lead Option (optional) LF = Lead Free LN = Lead Free Annealed Package Type F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
0601E--12/22/04
16
ICS932S203
N
c
SYMBOL
L
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 0.05 0.80 0.17 1.20 0.15 1.05 0.27 .002 .032 .007 .047 .006 .041 .011
INDEX AREA
E1
E
A A1 A2 b c
12 D
a
D E E1 e
0.09 0.20 SEE VARIATIONS 8.10 BASIC 6.00 6.20
.0035 .008 SEE VARIATIONS 0.319 .236 .244 0.020 BASIC .018 .30 SEE VARIATIONS 0 8 .004
0.50 BASIC 0.45 0.75 SEE VARIATIONS 0 8 0.10
A2 A1
A
L N
-C-
aaa VARIATIONS N 56
e
b
SEATING PLANE
aaa C
6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil)
D mm. MIN 13.90 MAX 14.10 MIN .547
D (inch) MAX .555
7/6/00 Rev B
MO-153 JEDEC Doc.# 10-0039
Ordering Information
ICS932S203yGLFT
Example:
ICS XXXX y G Lx T
Designation for tape and reel packaging Lead Option (optional)
LF = Lead Free
LN = Lead Free Annealed Package Type G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
0601E--12/22/04
Prefix ICS, AV = Standard Device
17

▲Up To Search▲

Price & Availability of ICS9250-37

	To Download ICS9250-37 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .